Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory is used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. In some applications, the systems and devices may require that the instructions and/or data be retained in some form of a permanent/non-volatile storage medium so that the information is not lost when the device is turned off or power is removed. Exemplary applications include computer BIOS storage and diskless handheld computing devices such as personal digital assistants.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating gate transistors in a silicon substrate. A floating gate transistor is capable of storing electrical charge either on a separate gate electrode, known as a floating gate, or in a dielectric layer underlying a control gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
In order to program and/or erase a flash memory, typically a complex process must be followed. For example, before erasing a particular sector, that sector must be programmed (known as "pre-programming"). Erasing and programming sectors and cells involves complex application of high voltages to the memory cells for specified periods of time and in particular sequences. Many flash memories provide embedded state machines that perform the complex programming and erasing operations automatically. These processes of programming and erasing a flash memory may take a long time to complete. A typical erase sequence can take anywhere from 0.7 seconds up to 15 seconds. To erase an entire chip can take up to 49 seconds. While programming is much faster, on the order of 7 to 300 microseconds, it is still slow compared to other memory devices. Programming an entire chip can take up to 7 seconds (including the time to verify the data). Typically, standard Dynamic Random Access Memory ("DRAM") offers access times on the order of nano-seconds, a difference between microseconds of many orders of magnitude.
This complex nature of programming and erasing flash memory devices leads to a major problem in that they do not provide sufficiently fast random access. For example, conventional flash memory devices typically do not allow a processor to perform a read operation while a program or erase operation is underway in the flash memory device. In most implementations, the processor is required to periodically poll a status register of the flash memory device to detect the end of the program or erase operation before initiating a read operation to the flash memory device.
Unfortunately, as noted above, the programming and erase cycle times for typical flash memory are orders of magnitude greater than acceptable write access times of a conventional random access main memory using, for example, Dynamic Random Access Memory ("DRAM"). Such long latencies associated with programming or erase operations can lock up the operating system and prevent the system from functioning for unacceptably long time intervals if the flash memory is the only memory in the electronic system. Some prior flash memories allow erase suspend operations in order to address this problem. Erase suspend allows the processor to pause an erase operation so another sector can be read. However, such memories typically still impose a suspend latency interval of several microseconds before a read operation can be initiated. A typical suspend latency interval is from 0.1 to 20 microseconds.
Prior systems may employ multiple flash memory devices in an attempt to prevent such operating system lock up. In such systems, the processor usually has read access to one of the flash memory devices while other flash memory devices are undergoing a program or erase operation. However, such systems typically suffer from high costs because multiple flash memory devices are implemented even though the capacity of a single flash memory device may accommodate the needs of the particular electronic device.
Another prior art system uses a flash memory in combination with an EEPROM memory. This system allows a read operation of one of the memories while writing to the other. However, the size of an EEPROM memory cell is significantly larger than that of a flash memory cell which reduces the amount of storage that can be placed on the memory chip. Further, there are significant design and manufacturing complexities involved with integrating two different memory technologies on the same chip. Therefore, a device that uses an EEPROM in combination with a flash memory will typically be more expensive both to design and manufacture.
In addition, programming and erasing a flash memory involves higher than normal voltages as compared to performing read operations. The use of these higher than normal voltages can cause problems when trying to implement the capability to simultaneously read while programming/erasing. Such problems include difficulties in distributing the high voltages required for the program and erase operations along with normal voltage for read operations and handling increased noise induced on the read sense outputs by the use of high voltages elsewhere within the device. Further, depending on the implementation, redundant logic may also be employed which introduces further complexities.
Recently a new type of flash memory has been developed that is capable of providing simultaneous read and write operations. This type of flash memory uses sliding bank architecture to give the flash memory the ability to perform simultaneous read and write operations. In this type of flash memory, the memory device is divided into two or more banks. Each bank includes a number of sectors and each sector includes a set of memory cells. Each bank has a respective decoder circuit that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command (program or erase), the internal state machine takes control and starts the program or erase operation. While one bank is busy with the program or erase operation, the other bank can be accessed for reading data.
For a detailed discussion of sliding bank architecture, see U.S. Pat. No. 5,867,430 entitled "BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING" and U.S. Pat. No. 5,847,998 entitled "NON-VOLATILE MEMORY ARRAY THAT ENABLES SIMULTANEOUS READ AND WRITE OPERATIONS", which are herein incorporated by reference.
As known to those skilled in the art, flash memory may be used to store various types of information. In general, the information can be divided into two categories, code and data. Code corresponds to program code that is used to execute various operations that the flash memory is capable of performing. Data generally corresponds to fields of data that changes more frequently than code. Because code rarely, if ever, changes in the lifetime of some devices, it is desirable to have the ability to write protect sectors that store code, while leaving some sectors unprotected. Providing a write protect function allows manufacturers to ensure that data does not mistakenly get written into a sector that is designated for code.
To that end, a need exists for a simultaneous operation flash memory that is capable of write protecting a respective sector or a group of sectors.